In order to guarantee long battery life in mobile equipment, it is essential to minimize power consumption during periods of operation and stand-by periods. A stand-by period is a time when the mobile equipment is powered, but not operating at its full power draw. Further, in order to fully exploit the latest integration capability using the latest process technology, such as a complete system on a chip, several factors must be in place, such as reduced heat generation, simplified packaging, improved device reliability compared to prior devices, and reduced power consumption during all periods of operation.
An effective way to reduce power consumption during operation is to decrease the power supply voltage, because the current consumption is approximately proportional to the square of the supplied voltage. When the power supply voltage is reduced, the power consumed is also reduced. However, a reduced power supply voltage produces a drastic degradation of device performance, because the turn-on threshold voltage (threshold) of the transistors of the devices is generally not reduced, in order to avoid an increased leakage during the stand-by periods. This gives less of a margin for error in a transistor switching voltage, as well as reduces the switching speed of the device. Because high speed is desirable in multimedia devices, and high data throughput of a multimedia device depends on switching speed of the components making up the device, reducing the power supply voltage generally results in slower, rather than faster devices.
Embedded SRAMs are fundamental components in many Ultra Large Scale Integrated (ULSI) circuits, which are used to make modern electronics and devices, including multimedia devices. SRAMs are important sources of power dissipation because they contain a large number of frequently accessed internal busses (word lines, bitlines, data lines, etc), that are heavily loaded by transistors and parasitic metal interconnected capacitances.
A standard SRAM cell 10 is shown in FIG. 1. The cell 10 consists of four central transistors 20, 22, 30 and 32, connected in a cross-coupled inverter, or "latch" configuration. Typically, the two load transistors 20, 30 are PMOS transistors, while the drive transistors 22 and 32 are NMOS. Two pass transistors 26, 36 allow read and write access to a data node DATA 28, and a data node DATA 38, respectively. Control gates of the two pass transistors 26, 36, are coupled together and to a word line WL, which connects to all of the pass transistors of the cells in one row. The pass transistor 26 is coupled to a bitline BL, while the pass transistor 36 is coupled to a bitline complement, BL. The bitlines BL and BL are common to all of the pass transistors in one column.
The data nodes DATA and DATA are outputs of the inverters, and store the data of the memory cell 10. Data is stored as the presence or absence of a certain voltage at the data nodes. Conventionally, a voltage that is near a power supply reference voltage, for instance a Vdd, is referred to as a logic "1", HIGH, or ON, while a voltage near a lower reference voltage, for instance a ground voltage, is referred to as logic "0", LOW, or OFF. The structure of the latch provides that the data nodes DATA and DATA are always logical complements of one another, meaning that, after the inverters have flipped and the data has latched, one node will be logic "1" while the other will be logic "0". Once the data is set at the data node DATA (and, consequently, the data complement is set at the data node DATA), it will remain there as long as the Vdd voltage is supplied to the cell 10.
To write data to the SRAM cell 10, one of the bitlines that is typically charged to Vdd (bitlines BL or BL) is discharged almost to ground, while the other is left at Vdd or allowed to float. Driving the selected bitline to ground causes the data to be loaded into the data nodes DATA and DATA. For example, assume the data node DATA is currently at logic "1", and it is desired to change it to logic "0". The line BL is brought to near ground, while the line BL stays at Vdd, or floats. The word line WL is brought high, turning on the pass transistors 26, 36. The DATA node DATA discharges, first through the line BL, then through the transistor 22. When the latch switches, transistors 20 and 32 are OFF, while transistors 22 and 30 are ON, bringing the data node DATA to ground, or logic "0" (because transistor 22 couples it to ground), and bringing the data node DATA to Vdd, or logic "1" (because transistor 30 couples it to Vdd). Following the write operation, the wordline WL is disabled, and the bitlines BL and BL are again pre-charged to Vdd for the next accesses.
The bitlines BL and BL are heavily loaded lines in the memory array, and, because the bitline BL has a large voltage swing during the writing of the array (almost from Vdd to ground), this standard writing operation uses a lot of power because the bitline must be first discharged, then re-charged. As seen in an SRAM device 100 of FIG. 2, the memory cell 10 is a small part of a memory cell array 50. A decoder 60 and data line multiplexer 70 couple to the array, providing the appropriate signals to write to and read from all of the memory cells 10 in the memory cell array 50. Control logic 80 accepts control and address signals, while the data I/O 90 accepts and presents the data written to or read from the memory cell array 50. It is plain to see that the bitlines BL and BL run throughout the memory cell array 50, and thus are have a heavily loaded lines.
Many techniques to reduce power consumption in SRAMs have been employed, such as reducing bitline voltage swing by utilizing current sensing circuits, or by pulsing word line selection signals. Also, in order to reduce loading, the memory array is often divided into local word and bitlines. However, all of these approaches require additional circuitry, and have had mixed results, reducing the overall power used.